MEMORY ORGANIZATION : CACHE MEMORY

Memory Organization : Cache Memory

WHAT DO WE WANT IN A MEMORY?

	Capacity	Latency	Cost
Register	1000’s of bits	10 ps	$$$$
SRAM	1-4 Mbytes	0.2 ns	$$$
DRAM	1-4 Gbyes	5 m	$
Hard disk*	100’s Gbytes	10 ms
Want?	2-10 Gbytes	0.2ns	Cheap!

Key Idea

Key Idea : Exploit “ Principle of Locality “

 Keep data used often in a small fast SRAM

·        called “CACHE”, often on the same chip as the CPU

  Keep all data in bigger but slower DRAM

·        called “Main Memory” , usually separate chip

         Access Main Memory  only rarely, for remaining data

        The reason this strategy works : LOCALITY

·        if you access someting now, you will likely access it again(or its neighbours) soon

CACHE ANALOGY

You are writing a term paper for your history class at a table in the library

·        As you work you realize you need a book

·        You stop writing, fetch the reference, continue writing

·        You don’t immediately return the book, maybe you’ll need it again

·        Soon you have a few books at your table, and you can work smoothly without needing to fetch more books from the shelves

·        The table is a CACHE for the rest of the library

Now you switch to doing your biology homework

·        You need to fetch your biology textbook from the shelf

·        If your table is full, you need to return one of the history books back to the shelf to make room for the biology book

TYPICAL MEMORY REFERENCE PATTERNS

* Memory Trace

    * Temporal Locality

* Spatial Locality

**Memory Trace – A temporal sequence of memory references (addresses) from a real program.

**Temporal Locality – If an item is referenced, nearby items will tend to be referenced again soon.

**Spatial Locality – If an item is referenced, nearby items will tend to be referenced soon.

Exploiting the Memory Hierarchy

= Approach 1 ( Cray, others): Expose Hierarchy

    Registers, main memory, disk each available as explicit storage alternatives

    Tell programmers : "Use them cleverly"

= Approach 2 : Hide Hierarchy

   Programming model : SINGLE kind of memory, single address space.

   Transparent to programmer : Machine AUTOMATICALLY assigns locations,              depending on runtime usage patterns. 

EXPLOITING THE MEMORY HIERARCHY

 CPU speed is dominated by memory performance 

* More significant than : ISA, circuit optimization, pipelining, etc.

TRICK #1 : Make slow MAIN MEMORY appear faster 

 * Technique : CACHING

TRICK #2 : Make small MAIN MEMORY appear bigger

* Technique : VIRTUAL MEMORY

MEMORY HIERARCHY LEVELS

Block (aka line) : unit of copying 

** May be multiple words

If accessed data is present in upper level

** Hit : access satistified by upper level

* Hit ratio : hits/accesses

If accessed data is absent

**Miss : block copied from lower level

*Time taken : miss penalty

*Miss ration : misses/accesses

  = 1 - hit radio

**Then accessed data supplied from upper level

Cache Memory

** Cache memory

-The level of the memory hierarchy closest to the CPU

Given accesses X,....., Xn-1,  Xn

DIRECT MAPPED CACHE

Location determined by address

Direct mapped : only one choice

* #line is a power of 2

* Use low-order address bits

TAGS AND VALID BITS

How do we know which particular block is stored in a cache location?

* Store block address as well as the data

* Actually only need the hight order bits 

* Called the tag

What if there is no data in a location?

* Valid bit : 1 = present, 0 = not present

  *  Initially 0                                              

Cache Example

** 8-blocks, 1 word/block, direct mapped

** Initial state

Cache Example

Post by Nur Amelina Hassan B031310041